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Home > chinese-english > "systolic array" in English

English translation for "systolic array"

脉动阵列
心动阵列


Related Translations:
systolic standstill:  心缩停止
systolic bulge:  收缩期突起
systolic chip:  心动结构芯片
systolic bruit:  收缩期杂音
systolic algorithm:  心动算法
systolic whoop:  收缩期喘息,收缩期吼声,收缩期枭鸣声收缩期吼声
systolic impulse:  收缩期搏动
systolic beat:  收缩期搏动
systolic emptying:  收缩期输出量心缩期排血
aortic systolic pressure:  主动脉收缩压
Example Sentences:
1.Rsa cryptoprocessor based on a redesigned systolic array
基于新型脉动阵列的rsa密码处理器
2.For intra prediction , the boundary pixels are reshuffled before feeding into the systolic array
对于内部预测,我们先将边界点重组后在丢入过滤器中。
3.7 wang c l , lin j l . systolic array implementation of multipliers for gf . ieee trans . circuits and systems ii , 1991 , 38 : 796 - 800
在有限场的各种运算之中,以加法运算最为简单,而以乘法指数及找乘法反元素等运算较为复杂。
4.Raac - rsa adopts improved systolic array to realize montgomery arithmetic and , in this way , finishes the cardinal arithmetic of rsa , i . e . multiple module
其中raac - rsa方案采用改进后的systolic阵列来实现变种的蒙哥马力算法,进而完成rsa的核心运算? ?乘模运算。
5.A novel and generic approach is presented to the hardware implementation of the rsa cryptoprocessor in deep submicro technology with a redesigned systolic array
长比特1024位以上数据的全局信号传输和乘法器的动态分割问题,对于rsa密码处理器的速度提高是非常重要的因素。
6.This paper revealed an optimized strategy to search for systolic array transformations for nested loops , when the upper and lower bound of inner index was affine functions of there outer loop indexes
对于多重循环中,当内层迭代的上下界为外层迭代的仿射函数时,介绍了搜索脉动变换的一个优化策略和相应的自动化算法。
7.This paper revealed an optimized strategy to search for systolic array transformations for nested loops , when the upper and lower bound of inner index was affine functions of there outer loop indexes
摘要对于多重循环中,当内层迭代的上下界为外层迭代的仿射函数时,介绍了搜索脉动变换的一个优化策略和相应的自动化算法。
8.To increase hardware utilization and minimize cost , we combine inter and intra prediction by a reprogrammable fir filter , which is further implemented with systolic array
利用在解码的过程中一个巨块不会同时利用到内部以及相互预测的特性,设计了一套既可以处理内部预测也可以处理相互预测单一硬体架构来增加硬体使用效率以及降低成本。
9.Improve on algorithms can enhance encoding / decoding performance . with pipeline and systolic array architectures adopted in the hardware implements , encoder / decoder based on fpga can work better
对编译码算法的改进有助于提高rs编译码器的性能,而利用fpga来实现rs编译码器,并采用流水线、心缩式阵列等优化结构,更能提高编译码器的性能。
10.The improved algorithm not only inherits the fast convergence trait from rls and realizable systolic array from qr _ rls , but also eliminates square - root operation and gets directly equalizer output signals from systolic array . so this algorithm has more simple operation , faster executing speed , less hardware resource and lower hardware cost . some different equalization algorithm are imitated on the qpsk communication system with multipath channel
其次对一些成熟的自适应均衡算法(如lms算法、 rls算法、 qr _ rls算法、逆qr _ rls算法)进行了分析;介绍了一种改进后的无平方根的qr _ rls算法,该算法不但继承了rls的快速收敛特性和qr _ rls算法的systolic阵列可实现性,还取消了qr _ rls算法的平方根运算,使算法在硬件实现时运行速度更快,占用资源也更少,同时该算法还可由systolic阵列直接得到均衡后的输出信号,运算量更小。
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